The present invention relates to reflow ball-grid-array mounted integrated circuit packages and to methods of attaching semiconductor chips and packages with solder bumps to substrates.
Packaged integrated circuits are advantageously mounted on printed circuit boards or motherboards using surface mount technology. A preferred form of this technology is known as ball grid array mounting, and includes forming conjugate planar arrays of mounting pads or contacts on surfaces of integrated circuits and circuit boards, and interconnecting the contacts using arrays of solder balls.
A conventional microelectronic assembly can comprise a packaged integrated circuit which is mounted on a printed circuit board by means of an array of electrically-conductive solder balls. The integrated circuit can have a variety of configurations. The circuit can comprise a ceramic substrate including one or more electrically insulative layers and electrical metallization layers. An integrated circuit chip can be attached to the top of the substrate and electrically interconnected therewith by wire bonds or the like. The chip and wire bonds are preferably environmentally protected from physical damage and contamination by an encapsulation formed of epoxy resin or the like.
Another conventional ball grid array mounting configuration comprises an integrated circuit which is mounted on the circuit board in the same manner as the integrated circuit. However, the circuit comprises a substrate having three layers, the top two layers of which are formed with aligned openings that define a cavity. The integrated circuit is mounted on top of the bottom layer in the cavity and interconnected with the substrate by wire bonds. The die faces away from the circuit board, whereby the configuration is known as "die-up" mounting. The cavity provides ease of wire bonding and improved cooling, and is likewise sealed by an encapsulation.
Another conventional assembly is known as "cavity down" or "die-down" mounting. In this assembly, an integrated circuit includes a substrate having two layers, with an opening formed in the bottom layer to define a cavity which faces the circuit board. The downwardly facing cavity is protected with encapsulation.
The number of electronic devices on each chip is increasing to handle more complex tasks, requiring additional traces or wiring to provide the needed connections. The traces are formed on the surfaces of the components passing between adjacent solder ball pads. The chips are also to be made smaller to increase their operating speed. These developments present design and manufacturing problems of routing the traces through narrower channels, thereby limiting chip capabilities.
These problems can be understood referring to FIGS. 1-4. FIG. 1 shows generally at 100 a prior art flip chip substrate showing the locations of an evenly spaced array of solder bumps 104 on a chip. Some have traces or wires 108 coming out of them as shown on this chip side, some have wires coming out on the other chip side, and some are power and ground pads and thus do not have wires coming out of them. The square 112 in the center represents VDD and VSS bumps. The wires 108 are shown routed between the pads or bumps 104 out the sides, away from the chip center. A simplified view of another prior art array of (circular) solder pads 116 is shown in isolation in FIG. 2 generally at 120.
The width of the space between adjacent pads (104 or 116) determines how many wires (108) can be routed therebetween. As an example, FIG. 3 shows pads 120, 124 having a 0.5400 millimeter diameter 128 and spaced with a 1.0000 millimeter pitch 132 therebetween. With a spacing 136 of 0.1350 millimeter, only three wires 140, 144, 148 can be routed between these pads 120, 124. (A 0.135 micron pitch is a reasonably manufacturable pitch on today's substrate technologies.) The circular pads (120, 124) cannot be made too small, because they must have a certain amount of surface area to maintain sufficient reliability. They cannot be too fragile, because they must be able to handle certain levels of shear forces. The part must be robust and manufacturable, and also large enough to accommodate the needed routing, preferably using standard substrate suppliers.
Spherical solder balls are reflow attached to respective ones of the circular pads 120, 124 of FIG. 3 (or 104 of FIG. 1 or 116 of FIG. 2). Then they are reflow attached at their opposite ends to round pads on another electronic structure. One of the resulting solder balls 152 is shown enlarged and in isolation for illustrative purposes in different views in FIGS. 4a-c. As shown, the ball 152 has a round, compressed and truncated configuration.
Another problem associated with prior art ball grid array configurations is that, due to the relatively small height of the solder balls, the arrays are susceptible to mechanical and thermal stresses which can result in an unacceptably high failure rate.